HOWTO: Minimizing Vcores and Operating Temps-must read
Well, guys I wrote up this procedure I used to minimize my vcores on my new x3360/P35-based system, and I thought I'd share it with folks. It's a systematic method anyone can use to arrive at a minimized set of vcores for a given multiplier and FSB value. The examples I present in this post are using my X3360/P35-based system. The data arenít made-up or fictitious for the examples; they are the real data I used to arrive at the stable system.
Also, anyone can use this method - even if not overclocking their system - to lower their respective CPU and MB temps. I should say that I also incorporated this into my C2D/C2Q Overclocking Guide as well, but I felt it could also be useful to folks as a stand-alone post/guide.
The goal of stress testing is two fold:
1) To arrive at a stress test stable system (>24 hours with no prime95 errors).
2) To minimize your vcores and thus minimize heat product both on your CPU but also on your NB/SB and other MB components.
Prime95 will run and every now and then it will check the values itís calculating using your processor to its internal standards since its torture testing using known values. Assuming you enable error checking, youíll be notified if your values differ indicating an instability. This is why it is IMPERATIVE that you enable error checking within Prime95; again, if you donít enable it, you WILL NOT be notified of errors!
Do so simply by going to the ďAdvancedĒ menu and enabling ďRound off Checking.Ē If the system isnít stable, it will report an error and stop stressing the core that gave the error.
Now that you picked your operating condition (i.e. 9x333 or 8.5x400, etc.) letís stabilize the system through stressing it with prime95. Just so you get an idea what to look for, Coretemp as well as Prime95 (double-check that you enabled round off error checking) and run the Torture Test>Large FFTs. Youíll wanna keep an eye on your system temps to make sure they donít exceed the redline so the chip doesnít get throttled (assuming you have thermal management enabled in your BIOS). All your cores should get stressed equally (look in the task manager to verify):
For your reference, hereís what an error from within prime95 looks like:
When/if you get an error (and you will), youíll need to either back off on the operating conditions (FSB or multiplier) or add some voltage to your vcores. Therein lies the challenge. Since you have four different vcores to select from, how do you know which one or which ones to adjust?
Itís now time to minimize your vcore settings. Reboot and go into the BIOSí section where you can control your CPU and MB voltages. Remember, different motherboard will call these variables different terms. The pic below is right out of my BIOS so you can see what DFI calls them, and what they mean:
CPU VID Control Ė The processor vcore, Iím not sure why DFI calls it ďCPU VID ControlĒ but whatever. From here on out, Iím going to call it Vcc since technically, the term VID is an entirely different concept (see this document, page 14 for more if you have an interest).
DRAM Ė The memory vcore.
SBCore Ė Southbridge vcore (might be called ICH in your board).
NBCore Ė Northbridge vcore (might be called MCH in your board).
VTT Ė Reference voltage (might be called FSB Termination voltage in your board). Itís used to terminate data lines between the MCH and CPU.
Some motherboards give the option for GLT reference controls. If you enable this youíre adding three additional variables to the mix and making your life more complicated. Unless youíre an extreme overclocker wanting to squeeze every single MHz out of your system, my advice is not to enable the GLT options. Iíd also caution you not to enable this option since there is tons of misinformation out there about these undocumented features.
If you must, here a few links that might help you understand how it works and give you some starting points, but I wonít be using them in this guide:
Adjusting [Advanced] Gunning Transceiver Logic (A/GTL+) Voltage Levels for Increased Front Side Bus (FSB) Signaling Margins and Overclocking.
DFI UT P35-T2R: Tweakers Rejoice!
Good thread (kinda long) but good info.
There are several approaches you can use to arrive at a stable, minimized set of vcores. I recommend that you start with lower vcore values and work your way up. Lower values will fail much faster than higher values thus making the process a bit quicker for you.
To start with, select a set of vcores that are kinda low and see if you can POST. How do you know where to start? Use trial and error at this point unless you know someone elseís settings to use as starting points. When in doubt, Iíd recommend that you start near the bottom of the scale. Here are some rough guidelines for setting your VTT:
1.2-1.3V - for a FSB of ~400 MHz.
1.4-1.5V Ė for a FSB of ~420-440 MHz (exceed 1.4V at your own risk with a 45nm chip)!
1.6V Ė for a FSB of ~440-475 MHz - use at your own risk with a 45nm chip!
You should be aware that newer 45nm fab chips are MUCH less tolerant toward high VTT than their 65nm predecessors. Anantech published their experience frying a QX9650 with high VTTís as an example.
Vcc Ė Initially, set within 200-400 mV of where the auto setting used (remember that you need a little more in the BIOS compared to what CPU-Z told you). Remember to consult Intelís processor finder to know where the upper-end of safety is for your processor (I believe the figures there correspond to the values CPU-Z is displaying, not what you set in the BIOS.).
DRAM Ė What ever the RAM manufacture recommends is a good starting point. Unless youíre really overdriving them, they shouldnít need more.
SBCore Ė Iíve always used the lowest setting, but I typically donít push my systems that hard (20-25 %). Youíre on your own here.
NBCore Ė Start off low, 1.33 or 1.37 and see if you need more. Also, a little bit can go a long way. My system is unstable @ 1.330V here but stable @ 1.370V which is a difference of only 40 mV (0.04V).
Here are the levels my Q6600 @ 9x333 uses to run stable:
Memory Voltage=2.100V CPU VCore=1.2625V FSB Termination=1.200V NB Vcore=1.25V SB Vcore=1.50V ICH Chipset=1.057V
Vcc=1.12500V SB 1.05V=1.070V NB Core=1.370V SB Core/CPU PLL=1.550V CPU VTT=1.310V
Once you select a baseline set, that will complete a POST, youíll want to start a more vigorous evaluation by changing the MB vcores one-at-a-time moving forward. If you change too many variables at once, youíll never be able to arrive at the stable settings. Confused? Donít be, just read on and after you see the examples, I think the process will seem clearer to you.
The basic process is to try different Vcc values keeping the other vcores constant. Run p95 at a given Vcc and record what happens after an arbitrary time point (10 to 15 min is good to start with). If Vcc level is stable for 15 min of p95, reboot and lower it a little and repeat. The goal is to find the minimum level that gives errors, then increase it until itís stable, then extend that time out to say 2-4 h. If itís still stable, further extend it to 10-14 h. You can probably call it ďstableĒ if you can run p95 for 24 h. If a setting fails after 4 h, increase it one notch or so and repeat until itís stable out to 24 h. You can then come back knowing this Vcc and try to lower one of the other vcores repeating the process. Yes, itís time consuming and yes, itís tedious, and yes, thatís a ****load of rebooting, but it works.
The key to this process is keeping a detailed record to help you achieve a stable system and troubleshoot which vcore to change Ė p95 errors are NOT always the fault of a low Vcc! Without these data, youíll have a tough time. So what do you keep track of here?
1) The MB vcores youíre using
2) The Vcc values youíre testing
3) Which core failed (prime95 tells you) and how long it took to fail
4) Any observations or comments you want to record for yourself
Here is an example minimizing vcores using my X3360/P35-based system. The data presented arenít fabricated to help illustrate the method; rather, they are the real data I used to arrive at the stable system.
Hardware specs for your reference:
On to it: in my first try, I set up my MB vcores and began testing Vcc starting low (I chose 1.12500V somewhat arbitrarily).
Keeping the motherboard vcores constant, I varied the Vcc starting out low and working up high. You may or may not get a stable system on your first set of iterations (probably not actually). If you do, youíll probably want to repeat keeping your stable Vcc but optimizing (minimizing) for one of the other vcores such as NB or VTT, etc.
Overclocking log, Iteration Set 1 Comments: Initial try DRAM 2.100V SBCore 1.55V NBCore 1.37V VTT 1.200V Vcc/Prime95 success or failure 1.12500V Failed on core 3 ~ 5 min 1.13750V Failed on core 0 ~ 28 min 1.15000V Failed on core 2 ~1 h 18 min 1.16250V Failed on core 1 ~ 4 h 4 min
For discussionís sake, letís say the same core failed repeatedly. This scenario is likely caused by a low Vcc (although it doesnít have to be). For you quad core users, cores 0/1 and cores 2/3 should be treated the same, so if you get some core 0 and core 1 failures, treat them like a single core failure as you consider this analysis.
So, I increased the NBCore a few notches and tried a few higher Vcc settings just to see if it was enough:
Overclocking log, Iteration Set 2 Comments: Added some NBCore DRAM 2.100V SBCore 1.55V NBCore 1.41V VTT 1.200V Vcc/Prime95 success or failure 1.16250V Failed on core 2 ~2 min 1.17500V Failed on core 1 ~3 min
Overclocking log, Iteration Set 3 Comments: Added some VTT and kept the higher NBCore DRAM 2.100V SBCore 1.55V NBCore 1.41V VTT 1.310V Vcc/Prime95 success or failure 1.17500V STABLE 15 min 1.16250V STABLE 15 min 1.15000V STABLE 15 min
Overclocking log, Iteration Set 4 Comments: Kept the VTT, lowered the NBCore DRAM 2.100V SBCore 1.55V NBCore 1.37V VTT 1.310V Vcc/Prime95 success or failure 1.15000V STABLE 2 h 1.13750V STABLE 30 min 1.12500V STABLE 1 h 1.07500V crashed p95 (n=2) 1.09375V crashed p95 (n=1) 1.10625V BSoD after 1+h 1.11875V STABLE 11 h 1.11250V Failed on core 0 ~ 1 h 8 min
Itís a little easier to visualize if you sort the Vcc from low to high. If you keep your log in a spreadsheet, you can easily sort them, here are the same data sorted by Vcc:
Overclocking log, Iteration Set 4 Comments: Kept the VTT, lowered the NBCore DRAM 2.100V SBCore 1.55V NBCore 1.37V VTT 1.310V Vcc/Prime95 success or failure 1.07500V crashed p95-program exited (n=2) 1.09375V crashed p95-program exited (n=1) 1.10625V BSoD after 1 h 1.11250V Failed on core 0 ~ 1 h 8 min 1.11875V STABLE 11 h 1.12500V STABLE 1 h 1.13750V STABLE 30 min 1.15000V STABLE 2 h
Overclocking log, Iteration Set 5 Comments: 1.11875V seemed stable, minimizing VTT DRAM 2.100V SBCore 1.55V NBCore 1.37V Vcc 1.11875V VTT/Prime95 success or failure 1.250V Failed on core 0 ~ 2 h 1.260V Failed on core 2 ~ 1 h 20 min 1.280V Failed on core 0 ~ 18 h 22 min 1.310V Failed on core 1 ~ 1 h 20 min
Overclocking log, Iteration Set 6 Comments: 1.11875V seemed flaky, so upped the Vcc and kept the higher VTT. DRAM 2.100V SBCore 1.55V NBCore 1.37V VTT 1.310V Vcc/Prime95 success or failure 1.125000V Stable 21 h 34 min
Okay! So maybe it was the Vcc after all since it ran for over 21-1/2 h before I stopped it. You could argue that thereís no difference between 18-1/2 h and 21-1/2 h and you would have a valid argument. This underscores the need to collect multiple data point per level as I mentioned in the beginning of this section (I told you it was quick Ďn dirty)!
Finally, I set out to essentially repeat my Iteration Set 5 minimizing the VTT with the slightly higher Vcc.
Overclocking log, Iteration Set 7 Comments: 1.12500V seemed stable, minimizing VTT DRAM 2.100V SBCore 1.55V NBCore 1.37V Vcc 1.12500V VTT/Prime95 success or failure 1.250V Failed on core 0 ~ 1 h 3 min 1.280V Failed on core 1 ~ 1 h 0 min 1.310V STABLE 34 h 41 min
To summarize, using a stepwise approach and documenting your runs, you should be able to arrive at a stable system (assuming your hardware can operate at the level you choice). It probably goes without saying that you will need to repeat this process if change your operating conditions (multiplier and FSB).
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