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  #21  
Old 05-06-2016
sith'ari sith'ari is offline
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Quote:
Originally Posted by GI_Joe View Post
De-rating + UPS compatibility, if UPS are common in your region
UPSs are very common in Greece, but what exactly do you mean by de-rating? can you specify a little?
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  #22  
Old 05-06-2016
GI_Joe GI_Joe is offline
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Hold-up time shrinks with heat. To test real-life hold-up time test at 35-45C to get a realistic case ambieent temp. HardOCP tests with 45C, no matter the derating, which is mean against lower rated PSUs. You could stagger that to be fairer: hold-up at 25C+30C+35C+40C+45C.
Users would get a clearer impression on the need for an additional UPS or not. This also varies by the countries grid reliability.
And manufacturers with a larger capacitance headroom would get rewarded by the results.
Plus the likely compatibility with stepped/simulated/true Sinewave UPS. Nobody tests all 3 types.
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  #23  
Old 05-06-2016
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Aris is coming to Computex? I did not see him scheduled by our EU marketing
Korinna is back from maternity leave next week.
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  #24  
Old 05-06-2016
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Originally Posted by -The_Mask- View Post
Liberated from the Germans today.
Your time must be very ahead of my time + you are celebrating VE Day on May 7 and not May 8. Regardless, the 6-year war in Europe concluded around now. Congratulations. If my father were alive, he would lift a glass with you.
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  #25  
Old 05-06-2016
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^^I was wondering the same thing. So UVP and PWR_OK drop voltage threshold are different values, and different circuits, correct?

It doesn't seem right that UVP would be set so low. One would think UVP would kick in around 11.4V. Does UVP kick in at a certain voltage, or does it measure a drop in voltage?

Also, realistically, even if the PWR_OK signal is dropped when the voltage is below 11.4V, let's say 10.8V, it's not quite the end of the world. If you look at page 23 of the ATX specification http://www.formfactors.org/developer...rm_Rev_1_2.pdf

It reads:
1. At +12V1DC peak loading, regulation at the +12V1DC and +12V2DC outputs can go to
10%.
2. At +12V2DC peak loading, regulation at the +12V1DC and +12V2DC outputs can go to
10%.


The spec also says in various locations:
12V2DC supports processor power requirements and must have a separate current limit and provide 13 A peak
current for 10 ms; minimum voltage during peak is > 10.8 VDC


So the ATX specifications states that the positive voltages can be +-10% during peak load for a small amount of milliseconds. So, taking that knowledge and applying it to AC_LOSS to PWR_OK holdup time, it should not be a problem if the 12V rail is dropped at 10.8V and if it's under 11.4V for a duration of 10ms (or even higher wouldn't really matter). Then again, if the PSU is under a lighter load, the PWR_OK signal gets dropped even later, so it could be under 11.4V for a longer duration then. Also, I think it's best if people avoid the word "holdup time" in general and specify exactly what holdup time they are talking about. Let's look at the different definitions/types of holdup times:

AC_LOSS to PWR_OK holdup time
AC_LOSS to DC_LOSS (VOLT_OUT_SPEC) holdup time
defined as duration of time PSU remains on during AC loss

All of them are not the same thing, yet they are all grouped under the term "holdup time". The first would be the duration of time when there is AC loss to when the PWR_OK signal is cut. The second would be the duration of time until the 12V rail goes out of spec (I'm not if 5V and 3.3V play a role). And the last would be the duration of time from AC loss until the PS_ON signal initiates and executes.

Last edited by turkey3_scratch; 05-06-2016 at 09:12 PM.
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  #26  
Old 05-07-2016
Stefan Payne Stefan Payne is offline
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Quote:
Originally Posted by quest for silence View Post
It's not friday: is there some party there?
Yeah, thursday was 'Vatertag' here and many people did not work...
Though there is some exeption for some areas (like the one I live in)...
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  #27  
Old 12-20-2016
cypherpunks cypherpunks is offline
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Quote:
Originally Posted by GI_Joe View Post
Quote:
Originally Posted by -The_Mask- View Post
But at least 1ms before the output voltages of the PSU go out of spec the PSU should drop the Power OK signal.
No, the PSU's eventually existing OVP and/or UVP protections would cause it to shut own into Latch mode. If no such protections, the PC's components would receive the out of spec voltages for as long as they can without shutting down/blowing up themselves. For the MBU and GPU, their VRMs would try to regulate the out of spec voltages for as long and much as they can.

The PG signal is not a protection. It is a "not that simple" "HELLO" from the PSU to the MBU, which has to answer that with a "I am awake". THEN only, the PSU releases its output in PS_ON mode, no matter how good or bad that output is, that is monitored by protections.
Your explanation mixes too much the purposes of PG & PS_On and their causes and effects. There is a whole lot more to it than I have time to write here.
No, in addition to its role during power-on, the PWR_OK signal is required by ATX specification to be pulled low a minimum of 1 ms before the DC rails go out of spec , i.e. fall to 95% of their nominal values. This is parameter T6 in Table 11 on page 18 of the ATX12V 1.31 specification. Figure 2 states the 95% figure twice.

1 ms seems like not much time, but it's enough time to finish a flash memory write cycle.

Parameter T5 in the same table says that PWR_OK must stay high for 16 ms after loss of AC power.

That said, this is a spec that almost nobody tests, so I don't expect good compliance to it. Since nobody can trust the falling edge of PWR_OK, nobody uses it, and because nobody uses it, nobody implements it properly...

Quote:
Originally Posted by turkey3_scratch View Post
  1. At +12V1DC peak loading, regulation at the +12V1DC and +12V2DC outputs can go to 10%.
  2. At +12V2DC peak loading, regulation at the +12V1DC and +12V2DC outputs can go to 10%.
In v1.31 this changes that to 5%. (Below table 5 on p. 14.)
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  #28  
Old 12-20-2016
GI_Joe GI_Joe is offline
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Cypherphunks, still, the original discussion made it sound like the PG Signal is the protection itself, but it is just the signal of states of PSU and MBU.
And that signal does not always come as written as in the DG.
Also a lot is unspecified still by the DG. The sequence of the Rise time is the main reason for PSU incompatibilities. MBU A is ok if 3.3V & 5V shoot up at the same time, MBU B wants 3.3V 5ms earlier but not stronger than 5V, etc..
The DG is just a target to shoot at. It is not the Bible/Koran/Torah/etc.. Even Intel does not follow it itself fully. "REQUIRED" is for ...
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  #29  
Old 12-21-2016
cypherpunks cypherpunks is offline
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Quote:
Originally Posted by GI_Joe View Post
Cypherphunks, still, the original discussion made it sound like the PG Signal is the protection itself, but it is just the signal of states of PSU and MBU.
I may have misunderstood. Your English is somewhat stilted, and it's hard to be sure I understand. You are right that PWR_OK only applies in the case of AC power loss. In the case of malfunction or overload (such as OVP or OCP), it is not required to give warning (or, indeed, to go low at all).

(I also agree that what the specification requires is irrelevant to PSU manufacturers, who only care about what the market requires.)
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  #30  
Old 01-08-2017
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I think this belong here:

The worst case scenario for testing overshoot is to remove (and apply of course) power with the PSU under full load. The same goes of course for hold-up time with only exception that you need to find the right phase when the bulk cap won't be fully charged (worst case scenario that is, for the hold-up time). You don't just simply remove AC power when ever you want but you have to do it in the right phase of the incoming AC voltage. The duration of the AC power removal doesn't play a role in finding the actually hold-up time, what matters the most is WHEN you will remove power. This is if you want to find the REAL hold-up time.


The worst case scenario for a PSU with a APFC converter is when its bulk cap(s) has just delivered load and begin to charge. This moment is when the incoming power, from the APFC converter, starts to increase and becomes equal to the power level that the PWM stage requires.

Considering that P = E x I = Vrms x Irms = Vrms x Vrms/R(load) = Vrms^2 / R(load) and the power that the PFC delivers instantaneously equals P(t) = V(t)^2 / R(load). By using the Vrms values (in order to be able to use the DC power equation) you have V(t)= Vrms= Vpk / sqrt(2). This is close to 45 and 135 degrees on the phase of the incoming AC signal.




Personally I use my AC source to achieve the right phase since it provides me the option to start/stop the PSU in an exact degree of a phase (not any more because the super expensive AC source is highly stressed). However I should note that the above doesn't apply on all PSUs. So I have to try different phase angles in order to record the lowest possible hold-up time. Needless to say that this is a painful (for my AC source) and long procedure. I made an arduino device back in the day with programmable phase for power cut/apply which worked like a charm.


Another interesting fact about hold-up time. Does anybody ever wondered why it is 17ms and not for example 15 or 19ms?

Well according to the standard forums set by the Server System Infrastructure (SSI) Forum the minimum hold-up time at fully rated output power is one cycle. So for 50Hz it should be 20 ms while with 60 Hz it is 16.66 ms or 17 ms. This means that with 50 Hz normally it should be higher. Personally I use 230V and 50Hz in order to keep compatibility with my previous database, although at some point I should probably run two tests, one with 115V and one 230V (but the day only has 24h).

Last edited by crmaris; 04-25-2017 at 06:32 AM.
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