PCI Express 2.0 base spec completed.

[kuhla]

source -->> http://www.eetimes.com/news/semi/sho...leID=196900895

SAN JOSE, Calif. — The PCI Special Interest Group announced Monday (Jan. 15) they have completed work on the base spec for PCI Express 2.0, doubling serial signaling rates on the interconnect from 2.5 to 5GHz.

The base spec should pave the way for silicon support for Express 2.0 as early as this fall by companies including Advanced Micro Devices, Intel Corp and NVidia. Because the SIG chose 5 GHz signaling, chip makers are generally able to use serializer/deserializers (serdes) that have already been proven in communications applications up to 6.25 GHz.

However, the SIG did not mention work on a separate electro-mechanical spec for adapter cards and motherboards. That effort seeks to ensure that existing PC boards will support the higher signaling rates, a potentially bigger challenge for the PC industry that runs on tight margins and lean costs. The board standard was running a few months behind the base spec in completion when the PCI SIG held its annual meeting here in June.

The 5GHz version of Express will initially be adopted for graphics whose performance is typically limited by I/O throughput. Some graphics designers may use the fast channels for unified memory systems that use one pool of DRAM to support both system and graphics memory.

Later, servers will adopt the faster interconnect as they migrate from 3 to 6 Gbit/second versions of the serial ATA and serial-attached SCSI storage links. In addition, multi-port controllers for Ethernet, Infiniband and Fibre Channel will want the faster system link.

"In today's world, applications are becoming more advanced and are requiring more bandwidth," said Al Yanes, PCI-SIG chairman and president, in a prepared statement. "This is the perfect time to release PCIe 2.0, which not only supports high-bandwidth applications such as high-end graphics, but also adds many new architectural enhancements."

The PCI Express 2.0 spec also includes a number of new features. Under the new spec, software can dynamically adjust the configuration and the speed of Express 2.0 links. Software is also notified in cases where hardware links automatically adjust their width or speed.

Another new feature is an access control capability to give software an ability to control packet routing on the interconnect. The feature prevents hackers from spoofing and re-routing data, primarily for peer-to-peer traffic.

The PCIe Base 2.0 specification is available online to member companies.

So does that mean the 8-pin is finalized or not?