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Thread: Preview: Corsair SF600 – 600W semi-fanless SFX unit @HWI

  1. #11
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    You got it all wrong: "However, heavy oscillations appear just before the unit shuts down. Their peaks are high above 12.60 V which is in violation of ATX specification."




    The limit is 10% (13.2V) and not 5% in this case. It mentions the "conditions" of table 5 meaning where you measure voltages and not the thresholds depicted in this table.

    Also you measured 12.6V while I measured 12.38V. I trust more the DSO-X 3024A and this is why I use it and not the Rigol DS2072A which I also have. Personally I only trust the Rigols to measure fan speed. And when it comes to measuring hold-up time even 0.1V difference can lead to wrong results.

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    That is no overshoot testing, that is hold-up time testing. You got it all wrong.
    3.2.9 Voltage Hold-up Time - REQUIRED
    The power supply should maintain output regulations per Table 5 despite a loss of
    input power at the low-end nominal range-115 VAC / 47 Hz or 230 VAC / 47 Hz – at
    maximum continuous output load as applicable for a minimum of 17 ms
    Table 5 specifies the ordinary +-5 % regulation we all know. Turn-off is something totaly different than "loss of input power". It is - as it states - when you turn the unit off via returning PWR On high in the middle of loading the unit.

    May be, may be not. Could be many other factors than just the O-scope itself. Usually 0.1 V difference is about 0.05-0.1 ms. Nothing to write home about as I count whole miliseconds in my evaluation. Some of the peaks were as high as 13 V so even if it was 0.1 V lower it would still be out of spec.

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    For starters we don't do a competition here, I am just trying to give you an insight. If you don't want/need it then I won't bother again. It is good to have open ears though, if you really want to learn something new. This applies to me and all of us of course and not only you.

    You remove input power, simply as that, in both cases. Whether you do it for hold-up testing or overshoot testing it is EXACTLY the same. This is clearly a voltage overshoot and falls into the 3.3.7 paragraph.

    So during your hold-up tests you simply turn-off the PSU? You don't suddenly remove input power as you should? I am sorry but I totally lost you there. Maybe it is the language barrier.


    0.1V difference definitely isn't 0.05-0.1ms.

    In the shot below 0.16V difference leads to around 1.8ms difference easily. However do notice that they didn't tune the power ok signal normally so the delay is clearly much less than 1ms. Now if your scope isn't properly tuned or inaccurate, it could easily see the 11.24V as 11.4V and measure the hold-up time wrong and assume that the delay with the power ok signal is >1ms, so it is ok.


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    I don't understand what are you trying to say with those overshoot and hold-up time testing things, sorry.

    As for that image, yes, in that case it is much more. However, I believe I have never seen such form yet. In all cases I can recall it was MUCH steeper.

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    yeap it happens some times, however it isn't so rare (this hold-up waveform). I have seen it so far more than a dozen times. The normal deviation however with 0.1-0.2V is close or/and above 1ms in the majority of cases.

    about the hold-up time and the overshoot. This is a typical overshoot scenario. ATX doesn't makes this crystal clear so it is natural for anyone get confused (this isn't the first time that the ATX spec doesn't clear things out or needs some more clarifications to what it states).

    In any case they want to state that the thresholds on table #5 are to be taken into account mostly for the lower limit when it comes to the hold-up time. For the voltage overshoot you take the 10% raise over the nominal voltage. It is a matter of priorities. In the hold-up time test you mostly care about when the rails drop below the regulation limit while in the overshoot testing you don't want them to be high enough, to put the PSU and the system's parts in jeopardy. I believe those requirements haven't been thoroughly proofed by an engineer or they just slipped this part. E.g. they didn't completely remove #1 and #2 Notes in table 5, which are redundant now (used to be =+-10%).


    In any case we totally forgot that it is new Year's eve!

    Health, joy and happiness to all of you guys!!!

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    I would argue about that being overshoot, that's the thing. When I one day start testing overshoot at turn-on/turn-off scenarios, than sure, I already count on there is the 10% requirement.

    Here the norm states as quoted above: when the unit looses power, than it has to comply with table 5, that means 5% regulation. That is exactly what happened, it lost power.

    Now we can argue about the third test I do under the hold-up time section, that means interrupting the AC input for exact time (that is usually the PG signal HUT, the goal is to look what the unit does if the time of the AC loss is exactly the HUT of the PG signal), whether that is overshoot thus I should apply 10 %, or not. I would agree this is the situation where it may not be THAT clear though IMO it still falls under hold-up time testing thus 5 %.

    But testing hold-up time itself by removing AC input could not in any case be overshoot at turn-on/turn-off as this is simply not turn-on/turn-off situation. Trust me, one of my…interests…is administration law. So I think I (usually) understand how these things are written. And if I understand what you are trying to say, you are mixing two tests/requirements together.

    I've already covered the NY topic, so…

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    The worst case scenario for testing overshoot is to remove (and apply of course) power with the PSU under full load. The same goes of course for hold-up time with only exception that you need to find the right phase when the bulk cap won't be fully charged (worst case scenario that is, for the hold-up time). You don't just simply remove AC power when ever you want but you have to do it in the right phase of the incoming AC voltage. The duration of the AC power removal doesn't play a role in finding the actually hold-up time, what matters the most is WHEN you will remove power. This is if you want to find the REAL hold-up time.


    The worst case scenario for a PSU with a APFC converter is when its bulk cap(s) has just delivered load and begin to charge. This moment is when the incoming power, from the APFC converter, starts to increase and becomes equal to the power level that the PWM stage requires.

    Considering that P = E x I = Vrms x Irms = Vrms x Vrms/R(load) = Vrms^2 / R(load) and the power that the PFC delivers instantaneously equals P(t) = V(t)^2 / R(load). By using the Vrms values (in order to be able to use the DC power equation) you have V(t)= Vrms= Vpk / sqrt(2). This is close to 45 and 135 degrees on the phase of the incoming AC signal.




    Personally I use my AC source to achieve the right phase since it provides me the option to start/stop the PSU in an exact degree of a phase. However I should note that the above doesn't apply on all PSUs. So I have to try different phase angles in order to record the lowest possible hold-up time. Needless to say that this is a painful (for my AC source) and long procedure. I made an arduino device back in the day with programmable phase for power cut/apply which worked like a charm, however I prefer to use my AC source now.


    As a side note, as I can understand you state that you remove power for a period and then apply it again to check the hold-up time. Do you have any control on the phase when you will cut exactly the AC power? Also whether you remove power for a long period or for a small one, you still fall into what the paragraph 3.3.7 states since you remove the input voltage.


    Since we completely derailed the subject here. Another interesting fact about hold-up time. Does anybody ever wondered why it is 17ms and not for example 15 or 19ms?

    Well according to the standard forums set by the Server System Infrastructure (SSI) Forum the minimum hold-up time at fully rated output power is one cycle. So for 50Hz it should be 20 ms while with 60 Hz it is 16.66 ms or 17 ms. This means that with 50 Hz normally it should be higher. Personally I use 230V and 50Hz in order to keep compatibility with my previous database, although at some point I should probably run two tests, one with 115V and one 230V (but the day only has 24h).

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    You can get answer to all the questions if you actually had a look at the waveforms you comment, you can see that by naked yeye. Or better yet, had a look at what I use for this measurement in the first place. I got it covered quite well I think, link is in that very chapter you quote from.

    The worst case scenario for testing overshoot is to remove (and apply of course) power with the PSU under full load.
    Usually the worst things display under full load so…nothing that new?

    Anyway, regarding overshoot: even if I applied that on HUT testing, still overshoot has some definition. According to the general idea, here is overshoot:

    so that may be subject to 10% regulation; or here:

    while this is not overshoot:

    Or, to be precise, the first peak can be considered overshoot. But the regulation should handle that and return to normal, in worst case with some diminishing ringing. That what we can see here is some ringing/bad oscillation which is actually positivelly driven, getting worse; and it is not overshoot anymore, that's already plain bad regulation thus subject to 5% one which it does not pass.
    Last edited by Behemot; 01-01-2017 at 04:08 PM.

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    sorry I didn't have the time to look at your methodology. I am prepping for CES so my time is limited.

    I explained however how you should measure the hold-up time in order to be of help not only to you, but everyone that wants to do it properly. And I gave my insight to the voltage overshoot testing.

    In the first scope shot you provide, the spot you marked isn't an overshoot. The drops are called undershoots. The overshoot follows later in the screenshot. There is also lots of noise to your mains line, which probably is created by the device you use. This noise might affect the PSU's APFC converter.

    In the last scope shot I notice that the mains line isn't completely cut but there is still some voltage. Maybe your device allows a small amount of energy to pass through or your scope needs tuning.


    Anyway I am leaving for CES so I cannot keep up with this thread.

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    That's not undershoot actually, it's when the unit was already shutting down and the output caps were discharging, so the voltage started dropping to zero. Than, as the power was restored, overshot followed.

    Indeed, with some of the units such noise appears. That was deliberate modification (some kind of filter IIRC) to „soften“ the slope as some of the units especially without thermistors put some serios current spikes on the switching element. Once it was damaged by it.

    As for the remaining voltage, not sure what that is, maybe it's induced. Its enough to just touch a probe to induce some sine-wave voltage through the body, and here there is the AC separated only by some micrometers of few PN junctions. It's very small, 20-30 V max, always considered by the units as no voltage.

    While I agree that it would be best to always measure the units at their worst, and that may explain why some had so poor times (as I got close to their worst than with others)…the fact remains that quite a few even high-end units actually pass in spec. Most are under ATX requirements, some very badly. So the results could only be worse, not better. So I may try interrupting the power at different times (or, angles), though…the ATX itself states nothing about that and the units have to provide the power no matter when the interruption occurs. I mean, in reality it also happens randomly in any part of the cycle. And by always starting at 0, there is at least some continuity.

    Have a nice trip etc.

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