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Originally Posted by

**crmaris**
the worst condition for the hold-up time isn't when the AC voltage is 0? Not the peak or the low. @Travis?

The worst condition for APFC units is when the bulk capacitor just begins to charge, that is, when the energy coming from the PFC stage is increasing and equals the energy the PWM stage is requiring. Assume the average power PWM stage requires is roughly P=Vrms*Irms=Vrms*Vrms/R_load, and the instaneous power coming out of PFC stage is P(t)=v(t)*i(t)=v(t)*v(t)/R_load, so you get the result v(t)=Vrms=Vpeak/sqrt(2), which is, at (roughly) 45 degree phase and 135 degree phase of a line cycle. Neither zero point, nor the peak, just in between.

The thing is different for non-PFC and passive-PFC units, since the bridge rectifier only conducts in a short period near the peak (aka "conduction angle") , after which the bulk capacitor keeps discharging until another conduction. The worst condition will be the moment just before bridge rectifier conducts, which is several milliseconds before the peak.

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Those discussions above brings up another idea. The hold-up time test should find out the minimum hold-up time the UUT provides. So why not just cut off the AC input at various points of a line cycle and measure the hold-up time in each condition?

It's been a hard day's night and I've been working like a dog.