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Thread: Jonny reviews lack the Hold Up Time test.

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    I like the analog circuits because it can be very, very fast, without having to wait for software. Also, you don't have to rely on the accuracy/resolution of your ADC. I guess analog makes it very good at one thing, while digital makes it pretty good for a lot of things.

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    even an 8 bit ADC will be more than enough for this case.

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    the worst condition for the hold-up time isn't when the AC voltage is 0? Not the peak or the low. @Travis?

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    The AC is rectified by the BR and roughly filtered with (usually) a foil cap. You still get a large AC component, >20V on top of the DC output of the rectifier. When the AC input is zero, the output of the bridge rectifier, and thus the input to the PFC, might be 105VDC. At the positive or negative peak of the waveform, the output of the bridge rectifier might be 127VDC. The PFC is more efficient and may have more energy in the bulk cap when it has a higher input voltage. This effects the hold-up time by, usually, a couple milliseconds. Considering most high-end PSUs are in the range of 15-20ms hold-up time, 2ms can mean the difference between pass and fail.

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    Got my answer from another source. There is probably a phase difference so when the AC waveform is ats peak it might be zero in the APFC. This is why we want to cut the power exactly at the peak or the low. However I am not dead sure.

    Be as it may we still want to measure the hold-up time under the worst possible condition. This with a quick look is the zero point in voltage (when the waveform is at the zero point) but Travis if I recollect suggested peak or low. This is why I want his input in this, to confirm whether there is a phase difference between the input and the APFC and if this phase difference is consistent in every APFC converter.

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    Quote Originally Posted by CM Phaedrus View Post
    Well 1% is a baseline for me, if you're off by more than that then your reading is a bit suspect.

    I think this might be our solution though:
    http://www.opto22.com/site/pr_detail...=3&item=120A25
    Unfortunately, SSR is based on SCR and only cuts off when voltage crosses zero, but we don't want the input to be cut off at zero.
    It's been a hard day's night and I've been working like a dog.

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    Quote Originally Posted by crmaris View Post
    the worst condition for the hold-up time isn't when the AC voltage is 0? Not the peak or the low. @Travis?
    The worst condition for APFC units is when the bulk capacitor just begins to charge, that is, when the energy coming from the PFC stage is increasing and equals the energy the PWM stage is requiring. Assume the average power PWM stage requires is roughly P=Vrms*Irms=Vrms*Vrms/R_load, and the instaneous power coming out of PFC stage is P(t)=v(t)*i(t)=v(t)*v(t)/R_load, so you get the result v(t)=Vrms=Vpeak/sqrt(2), which is, at (roughly) 45 degree phase and 135 degree phase of a line cycle. Neither zero point, nor the peak, just in between.

    The thing is different for non-PFC and passive-PFC units, since the bridge rectifier only conducts in a short period near the peak (aka "conduction angle") , after which the bulk capacitor keeps discharging until another conduction. The worst condition will be the moment just before bridge rectifier conducts, which is several milliseconds before the peak.


    ----
    Those discussions above brings up another idea. The hold-up time test should find out the minimum hold-up time the UUT provides. So why not just cut off the AC input at various points of a line cycle and measure the hold-up time in each condition?
    It's been a hard day's night and I've been working like a dog.

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    so we don't want neither peak or 0. Then why you want it to make conduct at peak, from the moment there is an IC that can sense zero point AC level?

    However the best would be the 45 angle, right? Also I wonder why ATX spec doesn't state anything on the proper measurement of the hold-up time. They should give the right methodology for it, like they do for ripple and voltage regulation measurements.

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    Quote Originally Posted by crmaris View Post
    so we don't want neither peak or 0. Then why you want it to make conduct at peak, from the moment there is an IC that can sense zero point AC level?

    However the best would be the 45 angle, right? Also I wonder why ATX spec doesn't state anything on the proper measurement of the hold-up time. They should give the right methodology for it, like they do for ripple and voltage regulation measurements.
    It doesn't have to be cut off at peak. There are two options:
    1. All hold-up time tests are performed at the same phase angle.
    2. For every UUT we find out its MINIMUM hold-up time.
    It's been a hard day's night and I've been working like a dog.

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    I think I have our AC side designed.

    Relays won't work because of low speed and inconsistent arcing on open
    GTO Thyristors won't work because they're $500+
    SSRs won't work because they only turn off at one phase angle

    The solution is fairly simple: put a mosfet behind a bridge rectifier.



    The DC supply for the mosfet and its driver is a little clunky/overkill, but should work fine.

    A1 = gate driver signal
    A2 = AC voltage sense
    A3 = AC section DC supply


    The power mosfet may need snubbing, and we may want a MOV in there as well. But this is the gist of it.

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